1. Field of the Invention
This application relates generally to a microcontroller architecture and, more specifically, to a direct memory access (DMA) controller with channel width configurability support.
2. Description of the Related Art
In the late seventies, IBM produced the first personal computer, or PC. PCs quickly became very popular, and companies started developing hardware and software products to support the PC. In 1984, IBM announced the PC/AT computer which soon became a standard adopted by other companies developing PC-based products.
PC/AT compatibility is a standard with no true specification. Instead, the rapid growth of the personal computer industry around the PC/AT machine helped to define the standard. Manufacturers of PC/AT-compatible computers were unable to change this standard because of the huge installed base of software and hardware built for the original PC. Even IBM was helpless to change the standard they had initiated.
Fifteen years later, PC/AT-compatible computers are still being manufactured and sold. Although somewhat amorphous, the PC/AT compatibility standard may nevertheless be defined according to a few key components.
At a software level, PC/AT compatibility implies that a computer is able to run DOS and Windows(copyright). These programs require that a computer include very particular hardware and firmware, however.
First, a main processor, an Intel 8088 or compatible microprocessor, sits at the heart of a PC/AT-compatible system. Essentially, the purpose of the microprocessor is to read instructions from memory and perform the operations specified by the instructions. The operations that may be performed include internal operations such as executing math functions, reading data from external devices, or writing data to external devices.
Thus, to fulfill its purpose, the microprocessor in a computer is typically coupled to a memory and one or more external devices, known as peripheral devices. The coupling of memory and the peripheral devices to the microprocessor is achieved using one or more buses. An ISA bus, short for Industry Standard Architecture, connects one or more peripheral devices to the microprocessor and the memory of a PC/AT-compatible computer.
Other ISA bus features are commonly found in PC/AT computers. The ISA bus supports a 16M memory address space as well as a 1K input/output (I/O) address space. The ISA bus also supports 8-bit and 16-bit data widths. Further, dynamic sizing of the ISA bus is possible in PC/AT-compatible systems.
In order for the devices to communicate, a computer system includes one or more clock signals. The clock(s) enable the various devices to synchronize to one another so that the devices may properly communicate. Further, in a PC/AT-compatible computer system, a set of interval timers provides a programmable frequency source for hardware and software to exploit.
Coupled to the microprocessor by the ISA or other buses, peripheral devices from time to time required service from the microprocessor. In a PC/AT-compatible architecture, peripheral devices use interrupt request lines obtain the attention of the microprocessor. Logic which arbitrates between multiple interrupt requests to the microprocessor in a particular manner is also part of a PC/AT-compatible system.
The ISA bus further supports dynamic cycle timing control using a pin known as IOCHRDY. Also, typically by including an ISA connector, DMA channels and IRQs are provided external to the PC/AT-compatible computer, so that external devices may communicate with the microprocessor and memory.
Another feature of PC/AT-compatible systems is the presence of a real-time clock (RTC) and complementary metal oxide semiconductor (CMOS) random access memory (RAM), a type of low power memory. The RTC and CMOS RAM are connected to a battery such that when the system is powered down, stored information contained in CMOS RAM is retained.
I/O address mapping is fixed in PC/AT-compatible systems, and some PC/AT cards expect address aliasing because only 10 of the 16 available address bits are decoded. Standard PC/AT peripheral devices are direct-mapped in an I/O space from 0000h to 03FFh.
A PC/AT-compatible system includes a particular mapping of its memory, known commonly as dynamic random access memory (DRAM). DRAM is typically addressed in a linear fashion staring at 00000000h and ending at the top of DRAM. Such systems also include a read only memory (ROM) which typically includes firmware which performs a power-on self test (POST) when the computer is first turned on. Further, all PC/AT-compatible systems include firmware known as basic input output system (BIOS). (Without the BIOS in the ROM, DOS and Windows(copyright) would not run.) The BIOS provides programs, known as software interrupts, which enable an operating system and application programs to interact with peripheral devices, such as floppy and fixed disk drives, without having to address the hardware directly.
In a PC/AT-compatible system, the BIOS ROMs are mapped over the normal DRAM space. Thus, a windowing mechanism is required to redirect accesses to these spaces out to the ISA bus to access the ROM. Further, to support system management mode (SMM), which is common in many PC/AT computers today, an additional overlay DRAM region, accessible only to the processor, is provided. Additionally, several regions below the top of memory are decoded to support BIOS, expansion ROMs, and a video buffer. To recover these regions, typical PC/AT systems xe2x80x9cshadowxe2x80x9d these regions (i.e., copy the ROM contents to DRAM) for faster execution.
During system initialization, or POST, instructions are executed by the microprocessor. Because PC/AT-compatible systems are flexible enough to permit system expansion, POST typically includes programs to detect when new hardware has been added to the computer. For example, one of the requirements of POST is to determine the size of memory. Because of the vast array of DRAM types and speeds that are commercially available, a PC/AT-compatible system provides a mechanism to allow POST to determine the type of memory which populates the computer.
In addition to the ISA bus, most PC/AT-compatible systems today include a high performance peripheral component interconnect (PCI) bus. In particular, PCI buses are favored for connecting a video subsystem to the computer. For those PC/AT-compatible systems which implement a PCI bus, a PCI host bridge coupled between the processor bus and the PCI bus maintains a mirror image of the current DRAM size configuration register in order to properly respond to a PCI access. Having this information in the PCI host bridge permits targets on the PCI bus to react more quickly to a request.
For transfers between the peripheral devices and the memory, a PC/AT-compatible system includes logic known as direct memory access (DMA). DMA provides the capability for transfers to be made between peripheral devices and memory while the processor is executing instructions. A PC/AT-compatible system has particular requirements for how DMA channels are configured and organized. For example, the PC/AT supports fly-by DMA transfers only between memory and I/O devices. A fly-by data transfer is one in which data is copied directly from a target device to a requesting device without an intermediate storage step within the DMA device. Memory-to-memory DMA transfers are not supported.
A common device employed to implement DMA in a PC/AT system is the 8237 DMA controller. Originally designed for 8-bit peripherals, special logic is typically included so that the 8237 DMA controller can also service 16-bit peripheral devices. However, a specific DMA channel is only configured for either 8-bit operation or 16-bit operation; DMA address registers are limited to 24 bits; and DMA transfer count registers are limited to 16 bits. In a PC/AT system, three 16-bit channels and four 8-bit channels are supported.
A direct memory access (DMA) controller of a processor-based device provides a plurality of DMA channels configurable for a PC/AT compatible mode or an enhanced mode. The DMA channels can include three channels on a DMA xe2x80x9cmasterxe2x80x9d controller and four channels on a DMA xe2x80x9cslavexe2x80x9d controller. The DMA master controller and the DMA slave controller are connected in a cascade configuration. In a standard PC/AT compatible mode of the DMA controller, the four slave channels provide 8-bit DMA channels and the three master channels provide 16-bit DMA channels. In an enhanced mode of the DMA controller, each of the three DMA master channels and one of the DMA slave channels are individually configurable to be either 8-bit or 16-bit DMA channels. The plurality of DMA channels thus support DMA width configurability. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation.
A DMA controller according to the described embodiment can operate in a PC/AT compatible mode or an enhanced mode of a system. In the enhanced mode, the DMA controller can provide a 28-bit address space and a 24-bit transfer count. The 28-bit address space enables the DMA controller to address more data than a typical PC/AT compatible DMA controller is able to address. The 24-bit transfer count enables the DMA controller to transfer larger blocks of data than a typical PC/AT compatible DMA controller is able to transfer blocks of data that cross page boundaries.